1. Field of Invention The present invention generally relates to a method and device for controlling peripheral devices, and more particularly to a method and device for data transfer on a peripheral component interconnection (PCI) bus.
2. Description of Related Art
FIG. 1 show a computer system architecture using a peripheral component interconnect (PCI) system, including a central processing unit 10, a PCI bus 14, a system memory 11, a host bridge 12, and a plurality of PCI-compatible peripheral masters. The PCI-compatible peripheral masters, such as a graphic adapter 16a, expansion bus bridge 16b, local area network (LAN) adapter 16c, and small computer system interface (SCSI) host bus adapter 16d, etc, are connected to the PCI bus 14. Every master can send a request signal REQ to ask for permission to use the PCI bus 14.
An arbiter located in the host bridge 12 can issue a grant signal GNT to allow the master to use the PCI bus 14.
FIG. 2 is a timing diagram of various control signals illustrating a read transaction executed on a conventional (standard) PCI bus. Data transfer between the PCI-compatible devices (such as masters or the north bridge in a computer chipset) are controlled by the interface control signals. A cycle frame signal FRAME is asserted by an initiator (masters or north bridge) to indicate the beginning and duration of an access. When the FRAME signal remains at the low level, the data transaction is continuing. At this stage, a valid address will be present on the address/data AD bus during the address phase. A valid bus command satisfying the PCI specifications will also be present on, the command/byte enable CBE [3:0] lines, indicating to a target that the data transaction requested by the initiator. The 4-bits CBE lines are encoded into 16 different commands, which are well defined under the PCI specifications. After the valid address was issued, data to be transferred are placed on the address/data AD bus, which is called a data phase. During the data phase, the CBE lines are used as Byte Enables, which are valid for the entire data phase and determine which byte lanes carrying meaningful data. When the FRAME signal is deasserted, the transaction is in the final data phase or has been completed.
An initiator ready signal IRDY and a target ready signal TRDY are used to indicate whether the initiator and the target are ready for data transfer. During a write operation, the IRDY signal indicates that valid data is present on the AD lines. During a read operation, it indicates the initiator is prepared to accept data. Wait cycles are inserted until both the IRDY and TRDY are asserted together. As for the TRDY signal, it indicates that valid data is present on the AD lines during a read operation.
During a write operation, it indicates that the target is prepared to accept data. A stop signal STOP indicates that the current target is requesting the initiator to stop the current transaction
The duration to proceed and complete a data transfer on a PCI bus is called a bus transaction 20, including an address phase 22 followed by one or more data phases, for examples, 24a, 24b, and 24c. Every data phase 24a,/b/c further comprises a wait cycle 26a/b/c and a data transfer cycle 28a/b/c. 
To show how the PCI system works, a read transaction is illustrated by referencing to the various control signals in the timing diagram in FIG. 2. In cycle T1, a FRAME signal is asserted by the initiator to indicate that data transfer is under way. AD bus contains a start address to specify a target while the CBE contains a valid bus command during the address phase. During the data phase, the CBE contains valid byte enable information during the entire data phase, including 24a, 24b, and 24c. In cycle T2, which is the wait cycle 26a of the data phase 24a, IRDY is asserted by the initiator indicating that the initiator is ready to accept data, while the target is not yet ready for data transfer. In cycle T3, the target is ready to send data and asserts TRDY. When both IRDY and TRDY are asserted in data transfer cycle 28a, data is transferred between the initiator and the target. The target deasserts TRDY in cycle T4, indicating the end of this data transaction, and prepares data for the second data transfer cycle, which is the wait cycle 26b of the data phase 24b. In cycle T5, the target is ready for data transfer by asserting TRDY again. When both IRDY and TRDY are asserted in data transfer cycle 28b, data is transferred between the initiator and the target. When the initiator is not ready to complete the last transfer, IRDY is deasserted in cycle T6. Since TRDY is still asserted at this stage, thus, the wait cycle 26c is initiated by the initiator. The initiator is ready again in cycle T7 by asserting IRDY. When both IRDY and TRDY are asserted in data transfer cycle 28c, data is transferred from the target to the initiator, and an entire read transaction is completed.
Under the PCI specifications, for example, version 2.2, there is a delayed transaction method. The delayed transaction is used by targets that cannot complete the initial data phase within the requirements of this specification. There are two types of devices that will use the delayed transaction: I/O controllers and bridges. In general, I/O controllers will handle only a single delayed transaction at a time, while bridges may choose to handle multiple delayed transactions to improve system performance.
A conventional delayed transaction progresses to completion in three phases:
1. Request by the master.
2. Completion of the request by the target.
3. Completion of the transaction by the master.
During the entire delayed transaction process, the master will repeatedly issue request signals, retain the privilege to use the PCI bus, and continuously send polling signals to the target.
For a conventional delayed transaction in a PCI system, the master will repeatedly issue request signals to the PCI bus if a transaction is retried. The repeatedly issued requests to the PCI bus until data is ready for transfer results in low utilization of the PCI bus without substantial data transfer.
The present invention provides a delayed transaction method for a PCI system, in which time frame required between two consecutive data acquisition cycles can be reduced in a multiple delayed transaction. The responder in the delayed transaction method functions like a master, which can automatically transfer data to the initiator which issues the request. Also, when the responder is not ready for data transfer, a defer identifier can be generated, based on which data can be transferred to the initiator which issues the request when the data is ready. Furthermore, a device which implements the delayed transaction method for the PCI system is provided in the present invention.
In accordance with the foregoing and other objectives of the present invention, a delayed transaction method and system used in a PCI system are provided. The delayed transaction method includes an initiator and a responder connected to a PCI bus, through which data is transferred. The delayed transaction method comprises the steps as follows.
The initiator issues a first request signal to use the PCI bus to access data in the responder; When the responder accepts the first request signal but can not immediately respond to the first request signal, the responder generates a first defer identifier corresponding to the first request signal; The responder issues a stop signal and the first defer identifier; The initiator issues a second request signal to use the PCI bus to access data in the responder; When the responder accepts the second request signal but can not immediately respond to the second request signal, the responder generates a second defer identifier corresponding to the second request signal; The responder issues a stop signal and the second defer identifier; When the data is readily available to respond to the first request signal, the responder issues the first defer identifier to the initiator; The initiator prepares to transfer data based on the first defer identifier from the responder corresponding to the first request signal; When the initiator is ready, data transfer between the initiator and the responder begins corresponding to the first request signal; When data transfer corresponding to the first request signal between the responder and the initiator is completed and data is readily available corresponding to the second request signal, the responder issues only a second buffer identifier of the second defer identifier; Based on the second buffer identifier, data transfer between the initiator and the responder begins corresponding to the second request signal.
The first defer identifier includes a defer address and a first buffer identifier; the second defer identifier includes the defer address and a second buffer identifier. The defer address corresponds to the initiator, the first buffer identifier corresponds to a first transaction procedure within the responder, and the second buffer identifier corresponds to a second transaction procedure within the responder. When data transfer corresponding to the first request signal is completed, the initiator issues a stop signal to terminate the data transfer between the initiator and the responder corresponding to the first request signal.
In addition, hardware devices, which implement the delayed transaction method in the PCI system, are also disclosed, in which a FRAME signal is kept asserted while the buffer identifier on the CBE line is changed when data is readily available from the target (responder). Thus, time frame required between two consecutive data acquisition cycles in a multiple delayed transaction can be reduced.